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| CY24130 HOTLink IITM SMPTE Receiver Training Clock Features * Integrated phase-locked loop * Low-jitter, high-accuracy outputs * 3.3V operation Benefits * Internal PLL with up to 400-MHz internal operation * Meets critical timing requirements in complex system designs * Enables application compatibility Part Number CY24130-1 CY24130-2 Outputs 2 2 Input Frequency 27 MHz (Driven Reference) 27 MHz (Crystal Reference) Output Frequency Range 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) Logic Block Diagram XIN XOUT P PLL REFCLK S0 S1 S2 OSC. Q VCO OUTPUT MULTIPLEXER AND DIVIDERS CLKA VDDL VDD AVDD AVSS VSS VSSL Pin Configuration CY24130-1, -2 16-pin TSSOP XIN VDD AVDD S0 AVSS VSSL N/C CLKA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT S2 REFCLK VSS N/C VDDL S1 N/C Cypress Semiconductor Corporation Document #: 38-07711 Rev. ** * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised February 04, 2005 CY24130 Frequency Select Options S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 CLKA 27 36 54 148.50 74.25 OFF, pulled low OFF, pulled low OFF, pulled low REFCLK 27 27 27 27 27 27 27 27 Units MHz MHz MHz MHz MHz MHz MHz MHz Pin Description Name XIN VDD AVDD S0 AVSS VSSL N/C CLKA N/C S1 VDDL N/C VSS REFCLK S2 XOUT Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Reference Crystal Input. Voltage Supply. Analog Voltage Supply. Frequency Select 0. Analog Ground. VDDL Ground. No Connect. 27-/36-/54-/148.50-/74.25-MHz Clock Output (frequency selectable). No Connect. Frequency Select 1. Voltage Supply. No Connect. Ground. Reference Clock Output. Frequency Select 2. Reference Crystal Output. Leave floating for -1. Absolute Maximum Conditions Parameter VDD, AVDD VDDL TJ Description Supply Voltage I/O Supply Voltage Junction Temperature Digital Inputs Electro-Static Discharge Min. -0.5 - - AVSS - 0.3 2 Max. 7.0 7.0 125 AVDD + 0.3 - Unit V V C V kV Recommended Operating Conditions Parameter VDD/AVDDL/VDDL TA CLOAD fREF CLNOM Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Nominal Parallel Crystal Load Capacitance for -2 Min. 3.135 0 - - - Typ. 3.3 - - 27 18 Max. 3.465 70 15 - - Unit V C pF MHz pF Document #: 38-07711 Rev. ** Page 2 of 5 CY24130 DC Electrical Specifications Parameter[1] IOH IOL IIH IIL VIH VIL IVDD IVDDL Name Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Description VOH = VDD - 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VIH = VDD VIL = 0V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current Min. 12 12 - - 0.7 - - - Typ. 24 24 5 - - - 16 14 Max. - - 10 10 - 0.3 - - Unit mA mA A A V V mA mA AC Electrical Specifications Parameter[1] DC ER EF t9 t10 Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. CLKA Peak-Peak Period Jitter Min. 45 0.8 0.8 - - Typ. 50 1.4 1.4 100 - Max. 55 - - - 3 Unit % V/ns V/ns ps ms Test and Measurement Set-up VDDs 0.1 F DUT Outputs CLOAD GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definitions Note: 1. Not 100% tested. Document #: 38-07711 Rev. ** Page 3 of 5 CY24130 t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Lead-free CY24130ZXC-1 CY24130ZXC-1T CY24130ZXC-2 CY24130ZXC-2T 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel Commercial Commercial Commercial Commercial 3.3V 3.3V 3.3V 3.3V Package Type Operating Range Operating Voltage Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 4.90[0.193] 5.10[0.200] 51-85091-*A MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07711 Rev. ** Page 4 of 5 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24130 Document History Page Document Title: CY24130 HOTLink IITM SMPTE Receiver Training Clock Document Number: 38-07711 REV. ** ECN NO. 314514 Issue Date See ECN Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07711 Rev. ** Page 5 of 5 |
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